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? semiconductor components industries, llc, 2012 september, 2012 ? rev. 14 1 publication order number: mc74hc595a/d mc74hc595a 8-bit serial-input/serial or parallel-output shift register with latched 3-state outputs high ? performance silicon ? gate cmos the mc74hc595a consists of an 8 ? bit shift register and an 8 ? bit d ? type latch with three ? state parallel outputs. the shift register accepts serial data and provides a serial output. the shift register also provides parallel data to the 8 ? bit latch. the shift register and latch have independent clock inputs. this device also has an asynchronous reset for the shift register. the hc595a directly interfaces with the spi serial data port on cmos mpus and mcus. features ? output drive capability: 15 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7 a ? chip complexity: 328 fets or 82 equivalent gates ? improvements over hc595 ? improved propagation delays ? 50% lower quiescent power ? improved input noise and latchup immunity ? these devices are pb ? free, halogen free and are rohs compliant ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable http://onsemi.com marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g, = pb ? free package see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information soic ? 16 d suffix case 751b tssop ? 16 dt suffix case 948f 1 16 pdip ? 16 n suffix case 648 1 16 1 16 1 16 mc74hc595an awlyywwg 1 16 hc595ag awlyww hc 595a alyw 1 16 (note: microdot may be in either location)
mc74hc595a http://onsemi.com 2 logic diagram serial data input 14 11 10 12 13 shift clock reset latch clock output enable shift register latch 15 1 2 3 4 5 6 7 9 q a q b q c q d q e q f q g q h sq h a v cc = pin 16 gnd = pin 8 parallel data outputs serial data output pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 latch clock output enable a q a v cc sq h reset shift clock q e q d q c q b gnd q h q g q f ordering information device package shipping ? mc74hc595ang pdip ? 16 (pb ? free) 500 units / rail nlv74hc595ang* mc74hc595adg soic ? 16 (pb ? free) 48 units / rail nlv74hc595adg* mc74hc595adr2g soic ? 16 (pb ? free) 2500 tape & reel nlv74hc595adr2g* MC74HC595ADTR2G tssop ? 16 (pb ? free) nlv74hc595adtr2g* ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable.
mc74hc595a http://onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 35 ma i cc dc supply current, v cc and gnd pins 75 ma p d power dissipation in still air, plastic dip? soic package? tssop package? 750 500 450 mw t stg storage temperature ?65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip, soic or tssop package) 260 c v esd esd withstand voltage human body model (note 1) machine model (note 2) charged device model (note 3) >3000 >400 n/a v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. ?derating ? plastic dip: ? 10 mw/ c from 65 to 125 c soic package: ? 7 mw/ c from 65 to 125 c tssop package: ? 6.1 mw/ c from 65 to 125 c 1. tested to eia/jesd22 ? a114 ? a. 2. tested to eia/jesd22 ? a115 ? a. 3. tested to jesd22 ? c101 ? a. recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ? 55 + 125 c t r , t f input rise and fall time v cc = 2.0 v (figure 1) v cc = 4.5 v v cc = 6.0 v 0 0 0 1000 500 400 ns dc electrical characteristics (voltages referenced to gnd) symbol parameter test conditions v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c v ih minimum high ? level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 v v il maximum low ? level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 v v oh minimum high ? level output voltage, q a ? q h v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v ih or v il |i out | 2.4 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc595a http://onsemi.com 4 dc electrical characteristics (voltages referenced to gnd) symbol unit guaranteed limit v cc v test conditions parameter symbol unit 125 c 85 c ? 55 to 25 c v cc v test conditions parameter v ol maximum low ? level output voltage, q a ? q h v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 2.4 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 v oh minimum high ? level output voltage, sq h v in = v ih or v il ii out i 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v ih or v il |i out | 2.4 ma ii out i 4.0 ma ii out i 5.2 ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 v ol maximum low ? level output voltage, sq h v in = v ih or v il ii out i 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 2.4 ma ii out i 4.0 ma ii out i 5.2 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i oz maximum three ? state leakage current, q a ? q h output in high ? impedance state v in = v il or v ih v out = v cc or gnd 6.0 0.5 5.0 10 a i cc maximum quiescent supply current (per package) v in = v cc or gnd l out = 0 a 6.0 4.0 40 160 a ac electrical characteristics (c l = 50 pf, input t r = t f = 6.0 ns) symbol parameter v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c f max maximum clock frequency (50% duty cycle) (figures 1 and 7) 2.0 3.0 4.5 6.0 6.0 15 30 35 4.8 10 24 28 4.0 8.0 20 24 mhz t plh , t phl maximum propagation delay, shift clock to sq h (figures 1 and 7) 2.0 3.0 4.5 6.0 140 100 28 24 175 125 35 30 210 150 42 36 ns t phl maximum propagation delay, reset to sq h (figures 2 and 7) 2.0 3.0 4.5 6.0 145 100 29 25 180 125 36 31 220 150 44 38 ns t plh , t phl maximum propagation delay, latch clock to q a ? q h (figures 3 and 7) 2.0 3.0 4.5 6.0 140 100 28 24 175 125 35 30 210 150 42 36 ns t plz , t phz maximum propagation delay, output enable to q a ? q h (figures 4 and 8) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns t pzl , t pzh maximum propagation delay, output enable to q a ? q h (figures 4 and 8) 2.0 3.0 4.5 6.0 135 90 27 23 170 110 34 29 205 130 41 35 ns
mc74hc595a http://onsemi.com 5 ac electrical characteristics (c l = 50 pf, input t r = t f = 6.0 ns) symbol unit guaranteed limit v cc v parameter symbol unit 125 c 85 c ? 55 to 25 c v cc v parameter t tlh , t thl maximum output transition time, q a ? q h (figures 3 and 7) 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 31 18 15 ns t tlh , t thl maximum output transition time, sq h (figures 1 and 7) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns c in maximum input capacitance ? 10 10 10 pf c out maximum three ? state output capacitance (output in high ? impedance state), q a ? q h ? 15 15 15 pf c pd power dissipation capacitance (per package)* typical @ 25 c, v cc = 5.0 v pf 300 timing requirements (input t r = t f = 6.0 ns) symbol parameter v cc v guaranteed limit unit 25 c to ?55 c 85 c 125 c t su minimum setup time, serial data input a to shift clock (figure 5) 2.0 3.0 4.5 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns t su minimum setup time, shift clock to latch clock (figure 6) 2.0 3.0 4.5 6.0 75 60 15 13 95 70 19 16 110 80 22 19 ns t h minimum hold time, shift clock to serial data input a (figure 5) 2.0 3.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns t rec minimum recovery time, reset inactive to shift clock (figure 2) 2.0 3.0 4.5 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns t w minimum pulse width, reset (figure 2) 2.0 3.0 4.5 6.0 60 45 12 10 75 60 15 13 90 70 18 15 ns t w minimum pulse width, shift clock (figure 1) 2.0 3.0 4.5 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns t w minimum pulse width, latch clock (figure 6) 2.0 3.0 4.5 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns t r , t f maximum input rise and fall times (figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns
mc74hc595a http://onsemi.com 6 function table operation inputs resulting function reset serial input a shift clock latch clock output enable shift register contents latch register contents serial output sq h parallel outputs q a ? q h reset shift register l x x l, h, l l u l u shift data into shift register h d l, h, l d sr a ; sr n sr n+1 u sr g sr h u shift register remains unchanged h x l, h, l, h, l u u u u transfer shift register contents to latch register h x l, h, l u sr n lr n u sr n latch register remains unchanged x x x l, h, l * u * u enable parallel outputs x x x x l * ** * enabled force outputs into high impedance state x x x x h * ** * z sr = shift register contents d = data (l, h) logic level = low ? to ? high * = depends on reset and shift clock inputs lr = latch register contents u = remains unchanged = high ? to ? low ** = depends on latch clock input pin descriptions inputs a (pin 14) serial data input. the data on this pin is shifted into the 8 ? bit serial shift register. control inputs shift clock (pin 11) shift register clock input. a low ? to ? high transition on this input causes the data at the serial input pin to be shifted into the 8 ? bit shift register. reset (pin 10) active ? low, asynchronous, shift register reset input. a low on this pin resets the shift register portion of this device only. the 8 ? bit latch is not affected. latch clock (pin 12) storage latch clock input. a low ? to ? high transition on this input latches the shift register data. output enable (pin 13) active ? low output enable. a low on this input allows the data from the latches to be presented at the outputs. a high on this input forces the outputs (q a ? q h ) into the high ? impedance state. the serial output is not affected by this control unit. outputs q a ? q h (pins 15, 1, 2, 3, 4, 5, 6, 7) noninverted, 3 ? state, latch outputs. sq h (pin 9) noninverted, serial data output. this is the output of the eighth stage of the 8 ? bit shift register. this output does not have three ? state capability.
mc74hc595a http://onsemi.com 7 switching waveforms serial input a 50% 50% switch clock v cc gnd valid t su t h figure 5. shift clock output sq h t r t f v cc gnd 90% 50% 10% 90% 50% 10% t plh t phl t tlh t thl t w 1/f max reset output sq h shift clock t w 50% 50% 50% v cc gnd v cc gnd t phl t rec t su 50% 50% v cc gnd latch clock q a -q h outputs 50% t plh t phl t tlh t thl 90% 50% 10% v cc gnd v cc gnd shift clock latch clock figure 3. v cc gnd t w figure 1. figure 2. figure 4. figure 6. output q output q 50% 50% 90% 10% t pzl t plz t pzh t phz v cc gnd high impedance v ol v oh high impedance output enable 50% test circuits *includes all probe and jig capacitance c l * test point device under test output *includes all probe and jig capacitance c l * test point device under test output connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . 1 k figure 7. figure 8.
mc74hc595a http://onsemi.com 8 d r q sr a dq lr a d q sr b dq lr b r d q sr c dq lr c r d q sr d dq lr d r d q sr e dq lr e r d q sr f dq lr f r d q sr g dq lr g r d q sr h dq lr h r expanded logic diagram output enable latch clock serial data input a shift clock reset 13 12 14 11 10 15 1 2 3 4 5 6 7 9 q a q b q c q d q e q f q g q h serial data output sq h parallel data outputs
mc74hc595a http://onsemi.com 9 timing diagram shift clock serial data input a reset latch clock output enable q a q b q c q d q e q f q g q h serial data output sq h note: implies that the output is in a high ? impedance state.
mc74hc595a http://onsemi.com 10 package dimensions pdip ? 16 n suffix case 648 ? 08 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? a ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? t ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 0.25 (0.010) t b a m s s min min max max millimeters inches dim a b c d f g j k m p r 9.80 3.80 1.35 0.35 0.40 0.19 0.10 0 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 7 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 7 0.244 0.019 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 9 16 ? a ? ? b ? d 16pl k c g ? t ? seating plane r x 45 m j f p 8 pl 0.25 (0.010) b m m soic ? 16 d suffix case 751b ? 05 issue k 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint 16 89 8x
mc74hc595a http://onsemi.com 11 package dimensions tssop ? 16 dt suffix case 948f issue b ??? ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 mc74hc595a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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